As processors evolve, emphasis is increasingly placed on processor performance. In order to achieve faster performance, technological advances are being pursued with respect to both the scale of the processors as well as with more efficient completion of computing tasks.
In order for a processor to operate at a high frequency and a low power, efficient processing of information is critical. A sequence of instructions (i.e., an instruction stream) may be used by a processor, for example an X86 processor, to process information. Prior to decoding instructions, the start location of each instruction must be determined. Since the X86 architecture is a variable length instruction architecture, a large amount of resources are used to determine the start locations of instructions within an instruction stream. Once the instruction start locations are determined, they are used by the machine to more efficiently process information.
An instruction stream may be fed to a unit, such as a decode unit, that picks instructions from the stream and sends the instructions to other areas of the machine for execution. The identification of the byte length of each instruction, so that the start locations of the subsequent instructions may be determined, is a complex task. Thus, it is not efficient for the machine to re-process the instruction stream to determine the instruction lengths prior to picking instructions during subsequent iterations of the program. By storing the start locations of instructions within the instruction stream, the processing of subsequent iterations is more efficient.
Consequently, processors are routinely built to identify the start location of each instruction only once and store this information for use during subsequent iterations. Accordingly, it would be beneficial to provide a method and apparatus capable of making use of this information most efficiently while processing an instruction stream at a high frequency.